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octal, 16 - bit nano dac+ with i 2 c interface data sheet AD5675 rev. b document feedback in fo rm at ion f urn i sh ed b y an alo g de v ice s i s b e li e ve d to b e accu ra te and r el i ab le . how e ve r, no re sp o n si bi l it y i s a s su m ed by a na lo g d e v ic es fo r i t s u s e, no r fo r any in fr ing em en t s o f pa te nt s o r o th er rig ht s of th ird p ar ties that m ay r esu lt fro m it s u se. sp ec if ic ation s sub jec t to c hang e without notice. no lic en se i s gr an te d by imp l ica t ion or ot he r wi se und er an y pa ten t or p at ent rig ht s of an a log d ev ic e s. trademark s and register ed trademark s are the property of their respective owners. one tech no lo gy way , p . o. bo x 910 6, norwood, ma 0206 2 - 9106 , u.s .a. tel: 78 1.32 9.47 00 ? 2015 C 2016 analog devices, inc. all rights reserved. technica l support www.analog.com features high performance high relative accuracy (inl): 3 lsb maximum at 16 bits total unadjusted error (tue): 0.14% of fsr maximum offset error: 1.5 mv maximum gain error: 0.06 % of fsr maximum wide operating ranges ? 40c to +12 5c temperature range 2. 7 v to 5.5 v power supply easy i mplementation user selectable gain of 1 or 2 (gain pi n /bit ) 1.8 v logic compatibility i 2 c - compatible serial interface robust 2 kv hbm and 1.5 kv ficdm esd rating 20 - lead tssop and lfcsp rohs - c ompliant p ackage s applications o ptical transceivers base station power amplifiers process control (plc i nput/output cards ) industrial automation data acquisition systems general description the AD5675 is a low power, octal, 16 - bi t buffered voltage outpu t digital - to - analog conve rter (dac). the device includes a gain select pin, giving a full - scale output of v ref (gain = 1) or 2 v ref (gain = 2). the device operate s from a single 2.7 v to 5.5 v supply and is guaranteed monotonic by design. the AD5675 is available in 20- lead tsso p and lfcsp package s . the power - on reset circuit and a rstsel pi n ensure that the output d ac s power up to zero scale or midscale and remain there until a valid write takes place . the AD5675 cont ain s a power - down mode, reduci ng the current consumption to 1 a typical while in power - down mode. the AD5675 uses a versatile 2 - wire serial interface that operates a t clock rates up to 400 khz, and i ncludes a v logic pin intended for 1.8 v to 5 .5 v logic. table 1. octal nano dac+? devices interface reference 16 - bit 12 - bit spi internal ad5676r ad5672r external ad5676 not applicable i 2 c internal AD5675 r ad56 71 r functional block dia gram interface logic input register a0 a1 gn d v out 7 ldac sda scl AD5675 reset 2.5v ref v out 0 v out 1 v out 2 v out 3 v out 4 v out 5 v out 6 dac register string dac 0 buffer input register dac register string dac 1 buffer input register dac register string dac 2 buffer input register dac register string dac 3 buffer input register dac register string dac 4 buffer input register dac register string dac 5 buffer input register dac register string dac 6 buffer input register dac register string dac 7 buffer gain power-down logic power-on reset v logic v dd v ref rstsel gain 1/2 12550-001 figure 1 .
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AD5675 data sheet rev. b | page 2 of 26 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac characteristics ........................................................................ 5 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 16 ? theory of operation ...................................................................... 18 ? digital-to-analog converter .................................................... 18 ? transfer function ....................................................................... 18 ? dac architecture ....................................................................... 18 ? serial interface ............................................................................ 19 ? write and update commands .................................................. 20 ? i 2 c slave address ........................................................................ 20 ? serial operation ......................................................................... 20 ? write operation.......................................................................... 20 ? read operation........................................................................... 21 ? multiple dac readback sequence .......................................... 21 ? power-down operation ............................................................ 22 ? load dac (hardware ldac pin) ........................................... 22 ? ldac mask register ................................................................. 23 ? hardware reset ( reset ) .......................................................... 24 ? reset select pin (rstsel) ........................................................ 24 ? amplifier gain selection on lfcsp package ......................... 24 ? applications information .............................................................. 25 ? power supply recommendations ............................................. 25 ? microprocessor interfacing ....................................................... 25 ? AD5675 to adsp-bf 531 interface ........................................... 25 ? layout guidelines....................................................................... 25 ? galvanically isolated interface ................................................. 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26 ? revision history 8/2016rev. a to rev. b change to output noise spectral density parameter; table 3 ... 5 10/2015rev. 0 to rev. a added 20-lead lfcsp ....................................................... universal changes to features section and general description section ... 1 changes to table 2 ............................................................................ 3 change to table 5 ............................................................................. 7 added table 6; renumbered sequentially .................................... 9 change to figure 4 caption and table 6 title .............................. 8 added figure 5; renumbered sequentially and table 7 ............. 9 change to figure 19 caption ........................................................ 12 change to figure 33 ....................................................................... 14 change to table 8 ........................................................................... 19 change to read operation section .............................................. 21 changes to ldac mask register section and table 13 ............... 23 added amplifier gain selection on lfcsp package section, table 15, and table 16 .................................................................... 24 added figure 52, outline dimensions ........................................ 26 changes to ordering guide .......................................................... 26 1/2015revision 0: initial version
data sheet AD5675 rev. b | page 3 of 26 specifications v dd = 2.7 v to 5.5 v , 1.8 v v logic 5.5 v , r l = 2 k? , c l = 200 pf , a ll specifications t a = ?40c to +125c , unless otherwise noted. table 2. a grade b grade parameter min ty p max min ty p max unit test conditions/comments static performance 1 resolution 16 16 bits relative accuracy /integral nonlinearity (inl) 2 1.8 8 1.8 3 lsb gain = 1 1.7 8 1.7 3 lsb gain = 2 differential nonlinearity (dnl) 2 0.7 1 0. 7 1 lsb gain = 1 0.5 1 0. 5 1 lsb gain = 2 zero code error 2 0.8 4 0.8 1.6 mv gain = 1 or gain = 2 offset error 2 ?0.75 6 ?0.75 2 mv gain = 1 ?0.1 4 ?0.1 1.5 mv gain = 2 full - scale error 2 ?0.018 0. 28 ?0.018 0.14 % of fsr gain = 1 ?0.013 0. 14 ?0.013 0.07 % of fsr gain = 2 gain error 2 +0.04 0. 24 +0.04 0.12 % of fsr gain = 1 ?0.02 0. 12 ? 0 .02 0.06 % of fsr gain = 2 tue 0.03 0. 3 0. 03 0.18 % of fsr gain = 1 0.006 0. 25 0. 006 0.14 % of fsr gain = 2 offset error drift 2 , 3 1 1 v/c dc power supply rejection ratio (psrr) 2 , 3 0.25 0.25 mv/v dac code = mids cale , v dd = 5 v 10 % dc c rosstalk 2 , 3 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down (pe r chan nel) output characteristics 3 output voltage range 0 v ref 0 v ref v gain = 1 0 2 v ref 0 2 v ref v gain = 2 output current drive 15 15 ma capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k ? resistive load 4 1 1 k ? load regulation 183 183 v/ma v dd = 5 v 10%, dac code = midscale , ?30 ma i out +30 ma 177 177 v/ma v dd = 3 v 10%, dac code = midscale , ?20 ma i out +20 ma short - circuit curr ent 5 40 40 ma load impedance at rails 6 25 25 ? power - up time 2.5 2.5 s exiting power - down mode , v dd = 5 v reference in put reference input current 398 398 a v ref = v dd = v log ic = 5.5 v, gain = 1 789 789 a v ref = v dd = v log ic = 5.5 v, gain = 2 reference input range 1 v dd 1 v dd v gain = 1 1 v dd /2 1 v dd /2 v gain = 2 reference input impedance 14 14 k? gain = 1 7 7 k? gain = 2
AD5675 data sheet rev. b | page 4 of 26 a grade b grade parameter min ty p max min ty p max unit test conditions/comments logic inputs 3 input current 1 1 a per pin input voltage low , v inl 0.3 v log ic 0.3 v log ic v high , v inh 0.7 v log ic 0.7 v log ic v pin capacitance 3 3 pf logic outputs (sda ) 3 output voltage low, v ol 0.4 0.4 v i si n k = 200 a high, v oh v lo gic ? 0.4 v lo gic ? 0.4 v i sou rce = 200 a floating state output capacitance 4 4 pf power requirements v log ic 1.8 5.5 1.8 5.5 v i log ic 3 3 a power - on , ?40c to +105c 3 3 a power - on, ?40c to +125c 3 3 a power - down , ?40c to +105c 3 3 a power - down, ?40c to +125c v dd 2.7 5.5 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 7 1.1 1.26 1.1 1.2 6 ma ?40c to +85c 1.1 1.3 1.1 1.3 ma ?40c to + 12 5c all power - down modes 8 1 1.7 1 1.7 a tristate to 1 k?, ?40c to +85c 1 1.7 1 1.7 a power down to 1 k?, ?40c to +85c 1 2.5 1 2.5 a tristate to 1 k?, ?40c to +105c 1 2.5 1 2.5 a power down to 1 k?, ?40c to +105c 1 5.5 1 5.5 a tristate to 1 k?, ?40c to +125c 1 5.5 1 5.5 a power down to 1 k?, ?40c to +125c 1 dc specifications tested with the outputs unloaded, unless otherwise no ted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 , or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 256 to 65 , 280 . 2 see the terminology section. 3 gua ranteed by design and characterization ; not production tested. 4 together, channel 0, channel 1, channel 2, and channel 3 can source or sink 40 ma. similarly, together, channel 4, channel 5, channel 6, and channel 7 can source or sink 40 ma up to a junctio n temperature of 125c. 5 v dd = 5 v . the AD5675 include s current limiting to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operati on above the specified max imum operation junction temperature may impair device reliability. 6 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 ? typical channel res istance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 ? 1 ma = 25 mv. 7 interface inactive. all dacs active. dac outputs unloaded. 8 all dacs powered down.
data sheet AD5675 rev. b | page 5 of 26 ac characteristics v dd = 2.7 v to 5.5 v , r l = 2 k? to gnd , c l = 200 pf to gnd , 1.8 v v logic 5.5 v , a ll specifications t a = ?40c to +125c , unless otherwise noted. guaranteed by design and characterization; not production tested. table 3. parameter min ty p max unit test conditions/comments output voltage settling time 1 5 8 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital - to - analog glitch impulse 1 1.4 nv - sec 1 lsb change around major carry (gain = 1) digital feedthrough 1 0.13 nv - sec digital crosstalk 1 0.1 nv - sec analog crosstalk 1 ?0.25 nv - sec gain = 1 ?1.3 nv - sec g ain = 2 dac - to - dac crosstalk 1 ?2.0 nv - sec g ain = 2 total harmonic distortion ( thd) 1 , 2 ?80 db t a = 25c , bandwidth = 2 0 khz, v dd = 5 v, f out = 1 khz output noise spectral density (nsd) 1 80 nv/ hz dac code = midscale, bandwidth = 10 k hz , gain = 1 and 2 output noise 6 v p - p 0.1 hz to 10 hz , gain = 1 signal - to - noise rati o (snr) 90 db t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz spurious - free dynamic range (sfdr) 83 db t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio (sinad) 80 db t a = 25c , bandwidth = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. 2 digitally generated sine wave at 1 khz. timing characteristi cs v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, all specifications ? 40 c to +125 c , unless otherwise noted. table 4. parameter 1 , 2 min max unit description t 1 0.92 s scl cycle time t 2 0.11 s t high , scl high time t 3 0.44 s t low , scl low time t 4 0.04 s t h d ,sta , start/repeated start hold time t 5 40 ns t su ,d at , data setup time t 6 3 ? 0.04 s t hd,dat , data hold time t 7 ? 0.045 s t su ,sta , repeated start setup time t 8 0.195 s t su ,sto , stop condition setup time t 9 0.12 s t buf , bus free time between a stop condition and a start condition t 10 4 0 ns t r , rise time of scl and sda when receiving t 11 4 , 5 20 + 0 . 1 c b ns t f , fall time of scl and sda when transmitting/receiving t 12 20 ns ldac pulse width t 13 0.4 ns scl rising edge to ldac rising edge t 14 4.8 ns reset minimum pulse width low, 1.8 v v log ic 2.7 v 6.2 ns reset minimum pulse width low, 2.7 v v log ic 5.5 v t 15 132 ns reset activation time , 1.8 v v log ic 2.7 v 80 ns reset activation time , 2.7 v v log ic 5.5 v t sp 6 0 ns pulse width of suppressed spike c b 5 400 pf capacitive load for each bus line 1 see figure 2 and figure 3 . 2 guaranteed by design and characterization; not production te sted. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the minimum v ih o f the scl signal) to bridge the undefined region of the scl falling edge. 4 t r and t f are measured from 0.3 v dd to 0.7 v dd . 5 c b is the total capacitance of one bus line in picofarads . 6 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns.
AD5675 data sheet rev. b | page 6 of 26 timing diagrams scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 12550-002 figure 2. two-wire serial interface timing diagram reset t 14 t 15 v out x 12550-102 figure 3. reset timing diagram
data sheet AD5675 rev. b | page 7 of 26 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v log ic to gnd ?0.3 v to +7 v v out x to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v log ic + 0.3 v operating temperature range ?40c to +12 5c storage temperature range ?65c to +150c junction temperature 125 c reflow soldering pea k temperature, pb - free (j - std - 020) 260c esd ratings human body model (hbm) 2 kv field induced charged device model (ficdm) 1.5 kv stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affec t product reliability. thermal resistance the design of the thermal board requires close attention. thermal resistance is highly impacted by the printed circuit board (pcb) being used, layout, and environmental conditions. table 6. thermal resistance package type ja jb jc jt jb unit 20 - lead tssop (ru - 20) 1 98.65 44.39 17.58 1.77 43.9 c/w 20 - lead lfcsp (cp - 20 - 8) 2 82 16.67 32.5 0.43 22 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal te st board. se e jedec jesd51 2 thermal impedan ce simulated values are based on a jedec 2s2p thermal test board with nine thermal vias. see jedec jesd51. esd caution
AD5675 data sheet rev. b | page 8 of 26 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 1 1 v out 0 v dd v logic a1 a0 scl v out 1 v out 3 v ref reset rstse l ldac sda v out 6 v out 7 gain v out 5 v out 4 gnd v out 2 top view (not to scale) AD5675 12550-006 figure 4 . tssop pin configuration table 7. tssop pin function descriptions pin no. mnemonic description 1 v out 1 analog output voltage from dac 1 . the output amplifier has rail - to - rail operation . 2 v out 0 analog output voltage from dac 0 . the output amplifier has rail - to - rail operation . 3 v dd power supply input. the AD5675 operate s from 2.7 v to 5.5 v. decouple the v dd supply with a 10 f capacitor in parallel with a 0. 1 f capacitor to gnd. 4 v log ic digital power supply. the v oltage on this pin ranges from 1.8 v to 5.5 v. 5 scl serial clock line. this pin is used in conjunction with the sda line to clock data into or out of the 24 - bit input shift register . 6 a0 addre ss input. this pin s ets the first lsb of the 7 - bit slave address. 7 a1 address input. this pin s ets the second lsb of the 7 - bit slave address. 8 gain span set. when this pin is tied to gnd , all eight dac outputs have a span from 0 v to v ref . if this pin is tied to v log ic , all eight dac s output a span of 0 v to 2 v ref . 9 v out 7 analog output voltage from dac 7 . the output amplifier has rail - to - rail operation. 10 v out 6 analog output voltage from dac 6 . the output amplifier has rail - to - rail operation . 11 v out 5 analog output voltage from dac 5 . the output amplifier has rail - to - rail operation . 12 v out 4 analog output voltage from dac 4 . the output amplifier has rail - to - rail operation . 13 gnd ground reference point for all circuitry on the d evice. 14 rstse l power - on reset. tie this pin to gnd to power up all eight dacs to zero scale. tie this pin to v log ic to power up all eight dacs to midscale. 15 ldac load dac. ldac operate s in two modes, asynchronously and synchr onously . pulsing this pin low allows any or all dac registers to be updated if the input registers have new data, which allows all dac outputs to simultaneously update. this pin can also be tied permanently low . 16 sd a serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24 - bit input shift register. sda is a bidirectional, open - drain data line that must be pulled to the supply with an external pull - up resistor. 17 reset asynchronous reset input. the reset input i s falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, th e input register and the dac register are updated with zero scale or mid scale , depending on the state of the rstsel pin. 18 v ref reference in put voltage . 19 v out 3 analog output voltage from dac 3 . the output amplifier has rail - to - rail operation . 20 v out 2 analog output voltage from dac 2 . the output amplifier ha s rail - to - rail operation .
data sheet AD5675 rev. b | page 9 of 26 12550-005 14 13 12 1 3 4 reset 15 v ref sda ldac 11 gnd v dd scl 2 v logic a0 5 a1 7 v out 6 6 v out 7 8 v out 5 9 v out 4 10 nic 19 v out 1 20 v out 0 18 v out 2 17 v out 3 16 nic AD5675 top view (not to scale) notes 1. nic = no internal connection. 2. exposed pad. the exposed pad must be tied to gnd. figure 5 . lfcsp pin configuration table 8 . lfcsp function descriptions pin no. mnemonic description 1 v dd power supply input. the AD5675 operate s from 2.7 v to 5.5 v. decouple the v dd supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 2 v log ic digital power supply. the voltage on this pin ranges from 1.8 v to 5.5 v. 3 scl serial clock line. this pin is used in conjunction with the sda line to clock data into or out of the 24 - bit input shift register. 4 a0 address input. sets the first lsb of the 7 - bit slave address. 5 a1 address input. sets the second lsb of the 7 - bit slave address. 6 v out 7 analog output voltage from dac 7. the output amplifier has rail - to - rail operation. 7 v out 6 analog output voltage from dac 6. the output amplifier has rail - to - rail operation. 8 v out 5 analog output v oltage from dac 5. the output amplifier has rail - to - rail operation. 9 v out 4 analog output voltage from dac 4. the output amplifier has rail - to - rail operation. 10, 16 n i c no internal connect ion. 11 gnd ground reference point for all circuitry on the devi ce. 12 ldac load dac. ldac operates in two modes, asynchronously and synchronously. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data, which allows all dac outp uts to simultaneously update. this pin can also be tied permanently low . 13 sda serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24 - bit input shift register. sda is a bidirectional, open - drain data line that must be pulled to the supply with an external pull - up resistor. 14 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or midscale, depending on the state of the rstsel pin. 15 v ref reference in put voltage. 17 v out 3 analog output voltage from dac 3 . the output amplifier has rail - to - rail operation. 18 v out 2 analog output voltage from dac 2. the output amplifier has rail - to - rail operation. 19 v out 1 analog output voltage from dac 1. the output amplifier has rail - to - rail operation. 20 v out 0 analog ou tput voltage from dac 0. the output amplifier has rail - to - rail operation. epa d exposed pad. the exposed pad must be tied to gnd.
AD5675 data sheet rev. b | page 10 of 26 typical performance characteristi cs ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 10000 20000 30000 40000 50000 60000 70000 in l error (lsb) code 12550-007 figure 6 . inl error vs. code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10000 20000 30000 40000 50000 60000 70000 dn l error (lsb) code 12550-009 figure 7 . dnl error vs. code ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0 10000 20000 30000 40000 50000 60000 70000 tue (% of fsr) code 12550-0 1 1 figure 8 . tue vs. code ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 inl error (lsb) temperature (c) v dd = 5v t a = 25c 12550-013 figure 9 . i nl error vs. temperature ?40 ?20 0 20 40 60 80 100 120 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 dn l error (lsb) temper a ture (c) v dd = 5v t a = 25c 12550-015 figure 10 . dnl error vs. temperature 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 tue (% of fsr) temper a ture (c) v dd = 5v t a = 25c 12550-017 figure 11. tu e vs. temperature
data sheet AD5675 rev. b | page 11 of 26 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 in l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c 12550-025 figure 12. inl error vs. supply voltage ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 2.7 3.2 3.7 4.2 4.7 5.2 dn l error (lsb) supp l y vo lt age (v) v dd = 5v t a = 25c 12550-027 figure 13. dnl error vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 tue (% of fsr) supp l y vo lt age (v) v dd = 5v t a = 25c 12550-029 figure 14. tue vs. supply voltage ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temper a ture (c) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c 12550-031 figure 15. gain error and full - scale error vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 2.7 3.2 3.7 4.2 4.7 5.2 error (% of fsr) supp l y vo lt age (v) f u l l- s c a l e e rr o r g a i n e rr o r v dd = 5v t a = 25c 12550-033 figure 16. gain error and full - scale error vs. supply voltage ?0.6 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 ?40 ?20 0 20 40 60 80 100 120 error (mv) temper a ture (c) v dd = 5v t a = 25c o ff s e t e rr o r ze r o c od e e rr o r 12550-035 figure 17. zero code error and offset error vs. temperature
AD5675 data sheet rev. b | page 12 of 26 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.7 3.2 3.7 4.2 4.7 5.2 error (mv) supp l y vo lt age (v) v dd = 5v t a = 25c o ff s e t e rr o r ze r o c od e e rr o r 12550-037 figure 18. zero code error and offset error vs. supply voltage hits i dd full scale (ma) 0 20 40 60 80 100 120 0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01 v dd = 5v t a = 25c reference = 2.5v 12550-023 figure 19. supply current ( i dd ) histogram ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 v out (v) load current (a) s in k in g, v dd = ?2 .7v s in k in g, v dd = ?3 .0v s in k in g, v dd = ?5 .0v s o u rc in g, v dd = ?5.0v s o u rc in g, v dd = ?3.0v s o u rc in g, v dd = ?2.7v 12550-041 figure 20. headroom/footroom (v out ) vs. load current ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x8000 0x4000 0x0000 0xc000 12550-042 figure 21. source and sink capability at 5 v ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x0000 0x8000 0xc000 12550-043 figure 22. source and sink capability at 3 v 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0 10000 20000 30000 40000 50000 60000 70000 i dd (ma) code device 1 device 2 device 3 12550-044 figure 23. supply current (i dd ) vs. code
data sheet AD5675 rev. b | page 13 of 26 ?40 ?20 0 20 40 60 80 100 120 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i dd (ma) temper a ture (c) zero code externa l reference, ful l scale 12550-045 ful l scale figure 24. supply current (i dd ) vs. temperature 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 3.2 3.7 4.2 4.7 5.2 i dd (ma) supp l y vo lt age (v) ful l scale zero code externa l reference, ful l scale 12550-046 figure 25. supply current (i dd ) vs. supply voltage 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.7 3.2 3.7 4.2 4.7 5.2 input logic vo lt age (v) zero code ful l scale externa l reference, ful l scale i dd (ma) 12550-047 figure 26. supply current (i dd ) vs. input logic voltage 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) v dd = 5.5v gain = 1 1/4 to 3/4 scale 12550-048 da c 0 da c 1 da c 2 da c 3 da c 4 da c 5 da c 6 da c 7 figure 27. full - scale settling time ?0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 ?1 0 1 2 3 4 5 6 0 2 4 6 8 10 v out (v) v dd (v) time (ms) v dd (v) v out 0 (v) v out 1 (v) v out 2 (v) v out 3 (v) v out 4 (v) v out 5 (v) v out 6 (v) v out 7 (v) 12550-049 figure 28. power - o n reset to 0 v and midscale 0 0.5 1.0 1.5 2.0 2.5 3.0 ?5 0 5 10 v out (v) time (s) v dd = 5v t a = 25c mi d sc al e, g ai n = 2 mi d sc al e, g ai n = 1 12550-050 rese t figure 29 . exiting power - down to midscale
AD5675 data sheet rev. b | page 14 of 26 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 15 16 17 18 19 20 21 22 v out (v) time (s) v dd = 5v gain = 1 t a = 25c reference = 2.5v code = 7fff to 8000 energy = 1.209376nv-sec 12550-051 figure 30. digital - to - analog glitch impulse ?0.006 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h an n e l 1 c h an n e l 2 c h an n e l 3 c h an n e l 4 c h an n e l 5 c h an n e l 6 c h an n e l 7 12550-052 figure 31. analog crosstalk ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 0 2 4 6 8 10 12 14 16 18 20 v out (v) time (s) c h an n e l 1 c h an n e l 2 c h an n e l 3 c h an n e l 4 c h an n e l 5 c h an n e l 6 c h an n e l 7 12550-053 figure 32. dac - to - dac crosstalk ch1 5v m1.00s a ch1 401mv 2 1 12550-054 figure 33. 0.1 hz to 10 hz output noise plot 0 200 400 600 800 1000 1200 10 100 1k 10k 100k 1m nsd (nv/hz) frequenc y (hz) v dd = 5v t a = 2 5c ga in = 1 f u l l s c a l e m i d sc a l e z e r o s c a l e 12550-055 figure 34. noise spectral density (nsd) ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2 4 6 8 10 12 14 16 18 20 thd (dbv) frequenc y (khz) v dd = 5v t a = 25c 12550-056 figure 35. total harmonic distortion (thd) at 1 khz
data sheet AD5675 rev. b | page 15 of 26 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.10 0. 1 1 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 time (ms) c l = 0 n f c l = 0. 1 n f c l = 1 n f c l = 4. 7 n f c l = 1 0 n f v out (v) 12550-057 figure 36 . settling time vs. capacitive load 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 80 100 120 140 160 180 200 v out (v) time (s) da c 0 da c 1 da c 2 da c 3 da c 4 da c 5 da c 6 da c 7 12550-058 figure 37. settling time, 5.5 v 0 0.1 0.2 0.3 0 1 2 3 ?20 0 20 40 60 v out a t zero scale (v) v out a t midscale (v) time (s) rese t mi d sc al e, g ai n = 1 z ero s c al e, g ai n = 1 12550-059 figure 38. hardware reset ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x0000 0x8000 0xc000 12550-043 fi gure 39 . multiplying bandwidth
AD5675 data sheet rev. b | page 16 of 26 terminology relative accuracy or integral nonlinearity (inl) for a dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passin g through the endpoints of the dac transfer function. differential nonlinearity (dnl) d nl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified d nl of 1 lsb ma ximum ensures monotonicity. thi s dac i s guaranteed monotonic by design. zero code error zero code error is a measurement of the output error when zero code ( 0x0000) is loaded to the dac register. the ideal output is 0 v. the zero code error is always positive because the output of the d ac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero code error is expressed in mv. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. the ideal output is v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range (% of fsr) . gain error gain error is a measure of the span error of a dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift offset error drift is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the l inear region of the transfer function. offset error is measured with code 256 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) the dc psrr indicates how the output of the dac is affected by changes in the s upply voltage. psrr is the ratio of the change in v out to the change in v dd for the full - scale output of the dac. it is measured in mv/v. v ref is held at 2 v, a n d v dd is varied by 10%. output voltage settling time the output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change . digital - to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) . digital feedthrough digital feedthrou gh is a measur e of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec , and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. noise spectral density (nsd) n sd is a measurement of the internally generated random noise. random noise is characterized as spectral density (nv/hz). to measure nsd, load the dac to midscale and measur e the noise at the output. it is measured in nv/hz. dc crosstalk dc crosstalk is the dc change in the output level of one dac in respo nse to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while moni toring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has on another dac kept at midscale. it is expressed in v/ma. digital crosstalk digita l crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - s ec . analog crosstalk analog c rosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. to measure analog crosstalk, first load one of the input registers with a full - scale code change (all 0s to all 1s a nd vice versa). then , execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec . dac - to - dac crosstalk dac - to - dac c rosstalk is the glitch impulse transferre d to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa ), using the write to and update command s while mo nitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv - sec.
data sheet AD5675 rev. b | page 17 of 26 multiplying bandwidth the multiplying bandwidth is a measure of the finite bandwidth of t he amplifiers within the dac . a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sin e wave and its attenuated version using the da c. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. thd is measured in db.
AD5675 data sheet rev. b | page 18 of 26 theory of operation digital - to - analog converter the AD5675 is an octal, 16- bit, serial input, voltage output d ac . t he AD5675 operate s from a supply voltage of 2.7 v to 5.5 v. data is written to the AD5675 in a 24 - bit wo rd format via a 2 - wire serial interface. the AD5675 incorporate s a power - on reset circuit to ensure that the dac output powe r s up t o a kn own output state. the device also ha s a software power - down mode that reduces the t ypical current consumption to 1 a . transfer function the gain of the output amplifier is set to 1 or 2 using the gain select pin (gain) . when th e gain select pin is tied to gnd, all eight dac outputs have a span from 0 v to v ref . when the gain sele ct pin is tied to v logic , all eight dacs output a span of 0 v to 2 v ref . dac architecture the AD5675 implement s a segmented string dac architecture with an internal output buffer. figure 40 shows the internal block diagram. input register dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 12550-144 figure 40. single dac channel architecture block diagram the simplified segmented resistor string dac structure is shown in figure 41 . the code loaded to the dac register determines the node on the string where the voltage is tapped off and fed into th e output amplifier. the voltage is tapped off by closing one of the switches and connecting the string to the amplifier. because each resistance in the string has the same value, r, the string dac is guaranteed monotonic. r r r r r to output amplifier v r e f 12550-067 figure 41. resistor string structure output amplifier the output buffer amplifier generates rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, the offset error, and the ga in error. the gain pin selects the gain of the output . if the gain pin is tied to gnd, all eight outputs have a gain of 1, and the output range is 0 v to v ref . if the gain pin is tied to v logic , all eight outputs have a gain of 2, and the output range is 0 v to 2 v ref . thi s amplifier can driv e a load of 1 k? in parallel with 10 nf to gnd. the slew rate is 0.8 v/s with a typical ? to ? scale settling time of 5 s.
data sheet AD5675 rev. b | page 19 of 26 serial interface t he AD5675 use s a 2 - wire , i 2 c - compatible serial interface . th e device can be connected to an i 2 c bu s as a slave device under the control of the master devices . the AD5675 support s standard (100 khz) and fast (400 khz) data transfer mod es. support is not provided for 10- bit addressing and general call addressing. input shift register the input shift register of the AD5675 is 24 bits wide. data is loaded msb first (db23) , and the first four bits are the command bits, c3 to c0 (see table 9 ), f ollowed by the 4 - bit dac address bits, a3 to a0 (see tab l e 10 ), and finally , the 16- bit data - word. the data - word comprises a 16- bit input code (see figure 42 ). these data bits are transferred to the inpu t register on the 24 falling edges of scl. comm ands execute on individual dac channels, combined dac channels , or on all dacs , depending on the address bits selected . table 9 . command definitions command c3 c2 c1 c0 descripti on 0 0 0 0 no operation 0 0 0 1 write to input register n ( where n = 0 to 7, depending on the dac selected from the address bits in ta b l e 10 , d ependent on ldac ) 0 0 1 0 update dac register n wi th the contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up the dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 gain setup register (lfcsp package only) 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 update all channels of the input register simultaneously with the input data 1 0 1 1 update all channels of the dac register and input register simultaneously with the input data 1 1 0 0 reserved 1 1 1 1 reserved table 10 . address commands channel address , bits [3:0] selected dac channel a3 a2 a1 a0 0 0 0 0 dac 0 0 0 0 1 dac 1 0 0 1 0 dac 2 0 0 1 1 dac 3 0 1 0 0 dac 4 0 1 0 1 dac 5 0 1 1 0 dac 6 0 1 1 1 dac 7 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte a3 a2 a1 a0 12550-302 figure 42. input shift register content
AD5675 data sheet rev. b | page 20 of 26 write and update commands write to input register n (dependent on ldac ) command 0001 allows the user to write to the dedicated input register of each dac individually. when ldac is low, the input register is transparent, if not controlled by the ldac mask register. update dac register n with contents of input register n command 0010 loads the dac registers and outputs with the contents of the selected input registers and updates the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and updates the dac outputs directly. i 2 c slave address the AD5675 has a 7-bit i 2 c slave address. the five msbs are 00011, and the two lsbs (a1 and a0) are set by the state of the a1 and a0 address pins. the ability to make hardwired changes to a1 and a0 allows the user to incorporate up to four AD5675 devices on one bus (see table 11). table 11. device address selection a1 pin connection a0 pin connection a1 a0 gnd gnd 0 0 gnd v logic 0 1 v logic gnd 1 0 v logic v logic 1 1 serial operation the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition when a high to low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address. 2. the slave device with the transmitted address responds by pulling sda low during the ninth clock pulse (this is called the acknowledge bit, or ack). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its input shift register. 3. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). transitions on the sda line must occur during the low period of scl; sda must remain stable during the high period of scl. 4. after all data bits are read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge (nack) for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then high again during the 10 th clock pulse to establish a stop condition. write operation when writing to the AD5675 , begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the AD5675 require two bytes of data for the dac, and a command byte that controls various dac functions. three bytes of data must, therefore, be written to the dac with the command byte followed by the most significant data byte and the least significant data byte, as shown in figure 43. all these data bytes are acknowledged by the AD5675 . a stop condition follows. frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack by AD5675 ack by AD5675 sda r/w db23 a0a1 1 00 0 1 db22 db21 db20 db19 db18 db17 db16 19 9 1 ack by AD5675 ack by AD5675 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 12550-303 figure 43. i 2 c write operation
data sheet AD5675 rev. b | page 21 of 26 read op eration when reading data back from the AD5675 , begin with a s tart command followed by an address byte (r/ w = 0), afte r which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is a lso acknowledged by the dac. the user configur es the channel to read back the contents of one or more dac input registers and sets the readback command to active using the command byte. then , the master establishes a repeated start condition, and the addre ss is resent with r/ w = 1. this byte is acknowledged by the dac, indicating that it is prepared to transmit data. two bytes of data are then read from the dac, as shown in figure 44. a nack condition from the mas ter, followed by a stop condition, completes the read sequence. if more than one dac is selected, dac 0 is read back by default. m ultiple dac readback sequence when reading data back from multiple AD5675 dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the address byte must be fo llowed by the command byte, which is also acknowledged by the dac. the user selects the first channel to read back using the command byte. following this sequence , the master establishes a repeated start condition, and the address is resent with r/ w = 1. this byte is acknowledged by the dac, indicating that it is prepared to transmit data. the first two bytes of data are then read from dac input register n (selected using the command byte), msb first, as shown in f igure 44 . the next two bytes read back are the contents of dac input register n + 1 , and the next bytes read back are the contents of dac input register n + 2. data is read from the d ac input registers in this auto - incremented fashion until a nack followe d by a stop condition follows. if the contents of dac input register 7 are read out, the next two bytes of data read are the contents of dac input register 0 . frame 2 command byte frame 1 slave address 1 1 0 0 0 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack by AD5675 ack by AD5675 scl scl sda 1 9 9 1 1 9 9 1 ack by AD5675 repeated start by master ack by master frame 4 most significant data byte n frame 3 slave address ack by master nack by master stop by master frame 6 most significant data byte n + 1 frame 5 least significant data byte n 1 0 0 0 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 12550-304 figure 44. i 2 c read operation
AD5675 data sheet rev. b | page 22 of 26 power-down operation the AD5675 contains two separate power-down modes. command 0100 is designated for the power-down function (see table 9). these power-down modes are software programmable by setting 16 bits, bit db15 to bit db0, in the input shift register. there are two bits associated with each dac channel. table 12 shows how the state of the two bits corresponds to the mode of operation of the device. any or all dacs (dac 0 to dac 7) power down to the selected mode by setting the corresponding bits. see table 13 for the contents of the input shift register during the power-down/ power-up operation. table 12. modes of operation operating mode pd1 pd0 normal operation 0 0 power-down modes 1 k to gnd 0 1 tristate 1 1 when both bit pd1 and bit pd0 in the input shift register are set to 0, the device works normally with its normal power consumption of typically 1 ma at 5 v. however, for the two power-down modes, the supply current falls to typically 1 a. in addition to this fall, the output stage switches internally from the amplifier output to a resistor network of known values. this has the advantage that the output impedance of the device is known while the device is in power-down mode. there are two different power-down options. the output is connected internally to gnd through either a 1 k resistor, or it is left open-circuited (tristate). the output stage is shown in figure 45. resistor network v out x dac power-down circuitry amplifier 12550-071 figure 45. output stage during power-down the bias generator, output amplifier, resistor string, and other associated linear circuitry shut down when power-down mode is activated. however, the contents of the dac registers are unaffected when in power-down mode. the dac registers can be updated while the device is in power-down mode. the time required to exit power-down is typically 2.5 s for v dd = 5 v. load dac (hardware ldac pin) the AD5675 dacs have a double buffered interface consisting of two banks of registers: input registers and dac registers. the user can write to any combination of the input registers. updates to the dac registers are controlled by the ldac pin. instantaneous dac updating ( ldac held low) for instantaneous updating of the dacs, ldac is held low while data is clocked into the input register using command 0001. both the addressed input register and the dac register are updated on the 24 th clock, and the output changes immediately. deferred dac updating ( ldac is pulsed low) for deferred updating of the dacs, ldac is held high while data is clocked into the input register using command 0001. all dac outputs are asynchronously updated by pulling ldac low after the 24 th clock. the update occurs on the falling edge of ldac . scl dac register interface logic amplifie r ldac input register sda 16-bit dac v out x v ref 12550-072 figure 46. simplified diagram of input loading circuitry for a single dac table 13. 24-bit input shift register co ntents of power-down/power-up operation [db23:db20] db19 [db18:db16] dac 7 dac 6 dac 5 dac 4 dac 3 dac 2 dac 1 dac 0 [db15:db14] [db13:db12] [db11: db10] [db9:db8] [db7:db6] [d b5:db4] [db3:db2] [db1:db0] 0100 0 xxx 1 [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] [pd1:pd0] 1 x means dont care.
data sheet AD5675 rev. b | page 23 of 26 ldac mask register command 0101 is reserved for this hard ware ldac function. the a ddress bits are ignored. writi ng to the dac using command 0101 loads the 8 - bit ldac register (db 7 to db0). th e default for each channel is 0, that is, the ldac pin works no rmally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin. this flexibility is useful in applications where the user wants to select whi ch channels respond to the ldac pin. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 15 ). setting the ld ac bits ( db0 to db 7 ) to 0 for a dac channel means that th e update for this channel is controlled by the hardware ldac pin. table 14. ldac overwrite definition load ldac register ldac bits (db 7 to db0) ldac pin ldac operation 0000 0000 1 or 0 determined by the ldac pin. 1111 1111 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1. 1 x means dont care. table 15. write commands and ldac pin truth table 1 command description hardware ldac pin state input register content s dac register contents 0001 write to input register n ( d ependent on ldac ) v log ic data update no change (no update) gnd 2 data update data update 0010 update dac register n with the contents of input register n v log ic no change updat ed with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v log ic data update data update gnd data update data update 1 a high to low hardware ldac pin transition always updates the contents of the dac register w ith the contents of the input register on channels that are not masked (blocked) by the ldac mask register. 2 when ldac is permanently tied low, the ldac mask bits are ignored.
AD5675 data sheet rev. b | page 24 of 26 hardware reset ( reset ) the reset pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the rstsel pin. keep reset low for a minimum of 2 s to complete the operation (see figure 2 ) . when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. w hile the reset pin is low , t he outputs cannot be upda ted with a new value. a software executable reset function is also available that resets the dac to the power - on reset code. command 0110 is designated for this software reset function (see table 9 ) . an y events on ldac or reset during power - on reset are ignored. reset select pin (rs tsel) the AD5675 contain s a pow er - on reset circuit that controls the output voltage durin g power - up. by connecting the r stsel pin low, t h e output powers up to zero scale. note that this power - up is outside the linear region of the dac; by connecting the rstsel pin high, the v out x pins p ower up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. amplifier gain selec tion on lfcsp packag e the output amplifier gain setting for the lfcsp package is determined by the state of bit db2 in th e g ain setup register (see table 16 and table 17). table 16 . gain setup register bit description db2 amplifier gain setting db2 = 0 ; amplifier gain = 1 (default) db2 = 1 ; amplifier gain = 2 table 17 . 24 - bit input s hift register contents for gain setup command db23 (msb) db22 db21 db20 db19 to db3 db2 db1 db0 (lsb) 0 1 1 1 dont care gain reserved; set to 0 reserved; set to 0
data sheet AD5675 rev. b | page 25 of 26 ap plications informati on power supply recomme ndations the AD5675 is typically powered by the following supplies: v dd = 3.3 v and v logic = 1.8 v. the adp7118 can be used to power the v dd pin. the adp160 can be used to power the v logic pin. this setup is shown in figure 47 . the adp7118 can operate from input voltages up to 20 v. the adp160 can operate from inpu t voltages up to 5.5 v. adp160 ldo adp7118 ldo 5v input 1.8v: v logic 3.3v: v dd 12550-176 figure 47. low noise power solution for the AD5675 microprocessor inter facing micropr ocessor interfacing to the AD5675 is performed via a serial bus that uses a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 2 - wire interface consisting of a clock signal and a data signal. AD5675 to adsp - bf531 interface the i 2 c interface of the AD5675 is designed for eas y c onnect ion to industry - standard dsp s and microcontrollers. figure 48 shows the AD5675 connected to the analog devices, inc., blackfin? pro cessor. the blackfin processor has an integrated i 2 c port that can be connected directly to the i 2 c pins of the AD5675 . adsp-bf531 scl gpio1 ldac pf9 reset pf8 sda gpio2 AD5675 12550-077 figure 48. AD5675 to adsp - bf531 interface layout guidelines in any circuit where accuracy is important, careful considera - tion of the power supply and ground return layout helps to ensure the rated performance. d esig n t he printed circuit board ( pcb ) on which the AD5675 is mounted so that the device lie s on the analog plane. the AD5675 must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead t ype. the 0.1 f capacitor must have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to inte rnal logic switching. in systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the gnd plane on the device can be increased (as shown in fi gure 49 ) to provide a natural heat sinking effect. AD5675 gnd plane board 12550-078 figure 49. pad connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller a nd the unit being controlled to protect and isolate the controlling circuitry from any ha zardous common - mode voltages that may occur. i couple r? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the AD5675 makes the device ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 50 shows a 4 - channel isolated interface to the AD5675 using an adum1251 . for further information, visit www.analog.com/icoupler . 12550-079 encode decode encode decode decode encode sda scl to sda to scl adum1251 1 1 additional pins omitted for clarity. controller figure 50. isolated interface
AD5675 data sheet rev. b | page 26 of 26 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 51 . 20 - lead thin shrink smal l outline package [tssop] (ru - 20) dimensions shown in millimeters 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 020509-b bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.75 2.60 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 52 . 20 - lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.75 mm package height (cp - 20- 8 ) dimensions shown in millimeters ordering guide model 1 resolution (bits) temperature range accuracy package description package option AD5675a ruz 16 ?40c to +12 5c 8 lsb inl 20 - lead thin shrink smal l outline package [ tssop ] ru - 20 AD5675aruz - reel7 16 ?40c to +12 5c 8 lsb inl 20 - lead thin shrink smal l outline package [ tssop] ru - 20 AD5675b ruz 16 ?40c to +12 5c 3 lsb inl 20 - lead thin shrink smal l outline package [ tssop] ru - 20 AD5675b ruz - reel7 16 ?40c to +12 5c 3 lsb inl 20 - lead thin shrink smal l outline package [ tssop] ru - 20 AD5675a cpz - reel7 16 ?40c to +12 5c 8 lsb inl 20 - lead lead frame chip scale package [ lfcsp ] cp - 20 - 8 AD5675bcpz - reel7 16 ?40c to +12 5c 3 lsb inl 20 - lead lead frame chip scale package [lfcsp] cp - 20 - 8 eva l - AD5675sdz evaluation board 1 z = rohs compliant pa rt. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2 01 5 C 2016 analog device s, in c. all rights reserved. trademarks and registered trademark s are t he property of their respective owners. d 12550 - 0 - 8/16 ( b )

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